The present invention relates to a semiconductor device having pads. More particularly, the present invention relates to a semiconductor device in which a global step between an I/O region along the periphery of a chip and a central region of the chip is reduced even when the width of a metal line connected to a pad is increased.
In recent years, the degree of integration of a semiconductor integrated circuit has been increasing along with the advancement of minute processing techniques. A multilayer wiring structure is typically employed in an integrated circuit that is fabricated with a 0.25 xcexcm, or subsequent, design rule. Along with the miniaturization of devices, the thickness of each wiring film and interlayer insulating film in the multilayer wiring structure has been reduced. The reduction in the thickness of each wiring film also reduces the acceptable current density thereof.
A semiconductor integrated circuit typically includes I/O cells arranged along the periphery of the chip. An I/O cell includes a protection circuit for protecting the integrated circuit from an electrostatic discharge (ESD) and an input/output circuit. The width of each I/O cell has been reduced along with a reduction in the pad pitch due to an increase in the number of pins provided in an integrated circuit. Under such circumstances, for example, the acceptable current capacity of a metal line connected to the pad of an I/O cell, through which a large current is expected to flow, is increased by increasing the width thereof as much as possible, or providing the metal line in multiple layers, so as to increase the reliability thereof against possible wire breaking due to a current flow therethrough.
FIG. 8 illustrates a layout of a conventional semiconductor integrated circuit. More specifically, FIG. 8 illustrates an I/O cell having a three-layer wiring structure. The I/O cell includes ESD protection elements, output transistors, power supply lines and a pad. The output transistors all have the same structure, and also function as the ESD protection elements. Therefore, the term xe2x80x9coutput transistorsxe2x80x9d as used herein refers to both output transistors and ESD protection elements.
FIG. 9 is a cross-sectional view taken along line 101 of FIG. 8, and FIG. 10 is a circuit diagram illustrating the semiconductor integrated circuit of FIG. 8. A gate insulating film and an interlayer insulating film for providing an insulation between wiring layers are not shown in FIG. 8 and FIG. 9.
In FIG. 8 and FIG. 9, 102 denotes a p-type semiconductor substrate, and 103 and 104 respectively denote a p-type well and an n-type well, which are provided on the semiconductor substrate 102. Two NMOS transistors N101 are provided on the p-type well 103, and two PMOS transistors P101 are provided on the n-type well 104. The transistors N101 and P101 function as output transistors, and are separated from each other by a device separation region 105. In FIG. 8 and FIG. 9, 106 and 107 denote n-type diffusion regions, which respectively serve as the drain and the source of the NMOS transistors N101, and 108 and 109 denote p-type diffusion regions, which respectively serve as the drain and the source of the PMOS transistors P101.
Moreover, in FIG. 8 and FIG. 9, VSS denotes a power supply line at a ground potential which is provided in the second wiring layer, and VDD denotes a power supply line at a predetermined potential which is also provided in the second wiring layer. The power supply line VSS is connected to the n-type diffusion region 107, serving as the source of the NMOS transistors N101, via a via hole 110, an isolated wiring region 111 which is provided in the first wiring layer, and a via hole 112 (note that the two via holes 110 and 112 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction). The power supply line VDD is connected to the p-type diffusion region 109, serving as the source of the PMOS transistors P101, via a via hole 113, an isolated wiring region 114 which is provided in the first wiring layer, and a via hole 115 (note that the two via holes 113 and 115 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction).
Moreover, 122 denotes a pad, and 116 denotes a metal line having a large width which is provided in the first wiring layer. The metal line 116 is used to connect the output transistors N101 and P101 to the pad 122. The metal line 116 is connected to the n-type diffusion region 106, serving as the drain of the NMOS transistors N101, via a via hole 117, and to the p-type diffusion region 108, serving as the drain of the PMOS transistors P101, via a via hole 118. Furthermore, the metal line 116 is connected to the pad 122 via a via hole 119, an isolated wiring region 120 which is provided in the second wiring layer, and a via hole 121 (note that the two via holes 119 and 121 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction).
However, with the conventional I/O cell illustrated in FIG. 8 and FIG. 9, when the width of the metal line 116 is increased in order to increase the acceptable current capacity thereof, the parasitic capacitance between the metal line 116 in the first wiring layer and the power supply lines VSS and VDD in the second wiring layer may increase, thereby also increasing the delay time.
Moreover, when the width of the metal line 116 in the first wiring layer is increased in an I/O region along the periphery of the chip, the wiring area ratio of the first wiring layer in the I/O region (i.e., the ratio of the total area of wiring within a unit area, e.g., 100 xcexcmxc3x97100 xcexcm, with respect to the unit area) increases with respect to the wiring area ratio of the first wiring layer in the central region of the chip. The difference between the wiring area ratio of the first wiring layer in the I/O region and that in the central region of the chip may cause a physical step or unevenness (hereinafter, referred to simply as a xe2x80x9cstepxe2x80x9d) on the surface, even if the interlayer insulating film deposited on the first wiring layer is flattened through a CMP process (a chemical mechanical polishing process for increasing the flatness of a surface). The step increases as the difference in the wiring area ratio of the first wiring layer increases. Moreover, the step which is caused by the difference in the wiring area ratio of the first wiring layer and remaining after the CMP process will not be significantly reduced even after a CMP process that is performed in preparation for the formation of lines in the third wiring layer. The steps occurring in the respective wiring layers accumulate to cause a so-called xe2x80x9cglobal stepxe2x80x9d on the surface of the chip. Therefore, when the metal line 116 is provided as a multilayer line by using two or more wiring layers in order to further increase the acceptable current capacity, the global step between the I/O region and the central region of the chip increases. Typically, a plurality of chips are fabricated in a regular arrangement on a single wafer, and the I/O region of one chip adjoins the I/O region of another adjacent chip on the wafer. FIG. 11 illustrates an arrangement of a plurality of chips on a wafer. In FIG. 11, 150 denotes a wafer, and a plurality of chips 151 are arranged on the wafer 150. Each chip 151 includes an I/O region 152 surrounding a central region 153 of the chip. When fabricating such chips 151 each having the central region 153 surrounded by the I/O region 152, as illustrated in FIG. 11, the I/O region 152 of one chip on the wafer 150 adjoins that of another adjacent chip. Therefore, when the wiring area ratio in the I/O region 152 is significantly larger than that in the central region 153, a large area defined by two I/O regions 152 adjoining each other will have a large wiring area ratio on the wafer 150. As a result, a sufficient flatness cannot be ensured across a large area on the chip even by the CMP process, thereby causing a substantial global step on the chip surface. Then, it is difficult to ensure a desirable exposure margin in the lithography process.
Where a so-called xe2x80x9cPOE (PAD on Element)xe2x80x9d structure, in which the pad is located above an element such as an output transistor, is employed, a parasitic capacitance occurs between the pad and the power supply lines. Specifically, referring to FIG. 12 illustrating a cross-sectional view of an I/O cell having a POE structure, the pad 122 is located above the two power supply lines VDD and VSS, thereby causing a parasitic capacitance between the pad 122 and the power supply lines VDD and VSS, which causes an increase in the delay time.
An object of the present invention is to reduce the global step while increasing the acceptable current amount by increasing the width of the metal line connected to the pad, even when the width of the I/O cell is reduced. In addition, another object of the present invention is to suppress the parasitic capacitance occurring between the metal line connected to the pad and the power supply lines connected to the output transistors.
In order to achieved these objects, in the present invention, the metal line connected to the pad is provided in an upper wiring layer that is higher in position than a lower wiring layer in which the power supply lines connected to the output transistors are provided so that the wiring area ratio of the lower wiring layer is lower than that of the upper wiring layer, thereby effectively suppressing the occurrence of the global difference.
Specifically, a semiconductor device of the present invention includes: a plurality of wiring layers; an output transistor provided on a substrate; a power supply line provided in a predetermined one of the wiring layers for supplying a power to the output transistor; a pad for connecting an output of the output transistor to an external unit; and a metal line for connecting the output transistor to the pad, wherein: the metal line is provided in one of the wiring layers that is higher in position than another one of the wiring layers in which the power supply line is provided; and a wiring area ratio of the other wiring layer which is provided under the wiring layer in which the power supply line is provided is less than a wiring area ratio of the wiring layer in which the power supply line is provided.
In one embodiment, the plurality of wiring layers include three or more wiring layers; and the metal line for connecting the output transistor to the pad is provided in an uppermost one of the wiring layers.
In one embodiment, the output transistor includes a first-conductivity-type transistor and a second-conductivity-type transistor; the first-conductivity-type transistor includes a first-conductivity-type diffusion region which is connected to the metal line; the second-conductivity-type transistor includes a second-conductivity-type diffusion region which is connected to the metal line; and the predetermined one of the wiring layers includes a vacant region where the power supply line is not present, the vacant region existing above the first- and second-conductivity-type diffusion regions which are connected to the metal line.
In one embodiment, the first- and second-conductivity-type transistors are provided so that a longitudinal direction thereof is parallel to a width direction of the pad.
In one embodiment, the power supply line is provided so as to extend in parallel to the longitudinal direction of the first- and second-conductivity-type transistors.
In one embodiment, a via hole of a stacked via structure is provided so as to extend from each of the first- and second-conductivity-type diffusion regions to the vacant region in the predetermined one of the wiring layers, the via hole extending between the predetermined one of the wiring layers in which the power supply line is provided and the first- and second-conductivity-type diffusion regions of the first- and second-conductivity-type transistors which are connected to the metal line.
In one embodiment, a part of the metal line provided in the uppermost one of the wiring layers is used as the pad.
In one embodiment, the pad is located above the output transistor.
In one embodiment, the metal line is provided in two or more of the wiring layers that adjoin one another in a vertical direction.
As described above, in the present invention, the wide metal line having a large acceptable current capacity which is connected to the pad is provided in an upper wiring layer that is higher in position than a lower wiring layer in which the power supply lines are provided. Therefore, as compared to the case where the metal line is provided in a wiring layer that is lower in position than the wiring layer in which the power supply lines are provided, the wiring area ratio of the lower wiring layer is reduced. Therefore, the difference between the wiring area ratio of the lower wiring layer in the I/O region including the pad and that in the central region of the chip is suppressed, thereby suppressing the occurrence of the global step.
Moreover, in the present invention, the metal line connected to the pad may be provided in the uppermost wiring layer. Typically, the thickness of an insulating film provided between adjacent wiring layers is greater than another insulating film that is lower in position than the insulating film. Therefore, when the metal line is provided in an upper wiring layer, particularly the uppermost wiring layer, the spacing between the metal line and the power supply lines is increased, thereby suppressing the parasitic capacitance occurring between the metal line and the power supply lines.
Moreover, in the present invention, a predetermined wiring layer in which the power supply lines are provided includes a vacant region, where no power supply line is present. Therefore, an output transistor can be connected to the metal line, which is connected to the pad, via a straight vertical path extending through the vacant region, thereby simplifying the structure of the connecting path.
In addition, in the present invention, a so-called xe2x80x9cstacked viaxe2x80x9d structure, including a plurality of via holes that are stacked on one another and substantially aligned with one another in the vertical direction, is employed for connecting the output transistor to the metal line, which is connected to the pad. A line in the stacked via structure can be provided so as to extend only around the via holes without having to take into consideration the acceptable current capacity thereof. Therefore, the wiring area ratio of the lower wiring layer is reduced, thereby further suppressing the global step between the I/O region and the central region of the chip.
Moreover, in the present invention, a part of the metal line in the uppermost wiring layer may be used as the pad. Therefore, it is possible to suppress the parasitic capacitance occurring between the metal line and the pad while eliminating the need for a line for connecting the metal line to the pad.
Furthermore, in the present invention, when the POE structure in which the pad is located above the output transistors is employed, any part of the metal line may be used as the pad, thereby increasing the freedom in the location of the pad.
In addition, in the present invention, the metal line connected to the pad may be provided across a large area in the form of a multilayer line. Therefore, when employing an area pad structure in which the pad is located in the central region of the chip, the connection to the pad can be made only by extending an end portion of the metal line facing the central region of the chip toward the area pad, whereby it is possible to reduce the length of the extension of the metal line to the area pad.